1. Field of the Invention
The present invention relates to the field of thin film transistors and more particularly to the field of thin film transistor metallizations.
2. Background Information
Amorphous silicon (a-Si) thin film transistors (TFT's) are widely used in display and imager applications where arrays of small display elements or arrays of small sensor elements are densely packed utilizing the ability to fabricate thin film transistors on large area non-crystalline substrates. An inverted thin film transistor is a thin film transistor in which the gate metallization is disposed on the substrate, the gate dielectric is disposed on top of the gate metallization and adjacent portions of the substrate, the amorphous semiconductor material is disposed on top of the gate dielectric and the source/drain metallization is disposed on the amorphous semiconductor material. This structure is referred to as inverted because it is up-side-down relative to the structure of a typical field effect transistor (FET) fabricated in a body of monocrystalline semiconductor material--a structure which was also used for early thin film transistors.
Two different gate metallizations are preferred in prior art thin film transistors. These are titanium alone and a first layer of titanium with a second layer of molybdenum disposed thereon. The two layer Mo/Ti electrode structure is used in those applications where higher conductivity than that provided by titanium alone is required.
One of the reasons for the use of titanium as the gate dielectric material is that titanium provides excellent adhesion to most substrate materials. In particular, typical substrates are either glass or coated with silicon dioxide. Titanium provides excellent adherence to both these materials. In the fabrication of a typical prior art thin film transistor, the titanium of the gate electrode is deposited on the substrate by sputtering or other appropriate processes. Thereafter, if molybdenum is to be included in the gate electrode, the molybdenum is deposited on the titanium, preferably without breaking vacuum in the deposition apparatus. A photoresist layer is then formed over the gate metallization, the photoresist is patterned and the gate metallization is etched down to the substrate. Either wet or dry etchants may be used.
However, we have found that where dry etching such as reactive ion etching is employed, excessive gate to gate leakage results from residual titanium which the dry etching process does not remove. A brief wet etch in dilute HF after the completion of the dry etching of the gate pattern will remove this residual titanium from the substrate surface. This wet etching step is required even if the dry etching step has included overetching which etches into the silicon dioxide or glass of the substrate. This is apparently because of the tenacious nature of titanium oxide which results in an inability of the dry etching process to remove all the titanium. Where a dry etching process is employed which provides a slope on the side walls of the gate metallization, this subsequent wet etching step converts the relatively smoothly sloped sidewall of the gate metallization into a bumpy sidewall having a bumpiness on the scale of the titanium thickness and thus in the range of 500-4000.ANG.. As a consequence of this bumpiness, subsequently deposited dielectric layers have reduced or impaired integrity because the bumpiness of the sidewall results in uneven deposition of the dielectric layer thereover and may even result in voids, pinholes and gaps in that subsequently deposited layer. A further problem is prevention of etching of the substrate during patterning of the gate metallization. This carries with it the disadvantage that the height of the gate topography is increased as well as having the disadvantage of removing underlying silicon dioxide. Where the substrate itself is not glass, this underlying silicon dioxide is typically intentionally included in the structure to form a barrier between other portions of the substrate and the thin film transistor. Increasing the topography of the gate metallization (i.e. a greater difference between the level of the top of the gate metallization and the level of the surface on which it is disposed) increases the difficulty of producing adequate step coverage of the gate dielectric which is deposited subsequently. Even worse, the excessive removing of the underlying silicon dioxide could result in a reentry sidewall structure which is much more difficult for the subsequently deposited gate dielectric to cover adequately. Consequently, such removal of the silicon dioxide is a significant disadvantage.
An improved gate electrode structure and fabrication process is needed which results in smoothly sloping sidewalls on the gate metallization and eliminates or substantially reduces etching of the underlying substrate.